SIO2
The Playstation 2 uses SPI to talk to memory cards and controller port peripherals, SIO2 is the controller in charge of this task.
SIO2 Register Summary
| Register | Address | Access | Description |
|---|---|---|---|
| SIO2_MEM_FIFO_TX | 0x1f808000 | RW | 256 byte transmit FIFO |
| SIO2_MEM_FIFO_RX | 0x1f808100 | RW | 256 byte receive FIFO |
| SIO2_REG_CMD_QUEUE | 0x1f808200 | RW | 16 entry command queue |
| SIO2_REG_PORT0_CTRL0 | 0x1f808240 | RW | Controller 0 |
| SIO2_REG_PORT0_CTRL1 | 0x1f808244 | RW | Controller 0 |
| SIO2_REG_PORT1_CTRL0 | 0x1f808248 | RW | Controller 1 |
| SIO2_REG_PORT1_CTRL1 | 0x1f80824c | RW | Controller 1 |
| SIO2_REG_PORT2_CTRL0 | 0x1f808250 | RW | Memory card 0 |
| SIO2_REG_PORT2_CTRL1 | 0x1f808254 | RW | Memory card 0 |
| SIO2_REG_PORT3_CTRL0 | 0x1f808258 | RW | Memory card 1 |
| SIO2_REG_PORT3_CTRL1 | 0x1f80825c | RW | Memory card 1 |
| SIO2_REG_TX | 0x1f808260 | W | 8/16/32-bit transmit |
| SIO2_REG_RX | 0x1f808264 | R | 8/16/32-bit receive |
| SIO2_REG_CTRL | 0x1f808268 | RW | Control register |
| SIO2_REG_CMD_STAT | 0x1f80826c | R | Command status |
| SIO2_REG_PORT_STAT | 0x1f808270 | R | Port status |
| SIO2_REG_FIFO_STAT | 0x1f808274 | R | FIFO status |
| SIO2_REG_FIFO_TX | 0x1f808278 | RW | TX FIFO head and tail position |
| SIO2_REG_FIFO_RX | 0x1f80827c | RW | RX FIFO head and tail position |
| SIO2_REG_IRQ_STAT | 0x1f808280 | RW | Interrupt status |
| SIO2_REG_REMOTE_CTRL | 0x1f808284 | RW | For IOP rev >= 0x23 |
Command Queue (SIO2_REG_CMD_QUEUE)
Port Control 0 (SIO2_REG_PORT[0-3]_CTRL0)
Port Control 1 (SIO2_REG_PORT[0-3]_CTRL1)
Control register (SIO2_REG_CTRL)
Command status (SIO2_REG_CMD_STAT)
Port status (SIO2_REG_PORT_STAT)
These correspond directly to pins on the IOP. Only the SAS[0-1] traces are connected to the controller ports, and only on fat PS2's, these are all tied high on later hardware.